The present invention relates to power semiconductor devices for use in power converters, in particular, to bidirectional devices or reverse blocking devices having bidirectional blocking capability.
FIG. 12 is a partial sectional view showing a peripheral region of a conventional ordinary planar junction IGBT. In operation of the IGBT, reliability on voltage blocking capability is guaranteed only in one direction (forward blocking capability). Since a reverse blocking function is born by reverse blocking ability of a diode, reliability on reverse blocking capability of the IGBT itself is beyond the guarantee. When a forward bias voltage is applied between the emitter electrode 108 and the collector electrode 109 of the IGBT with the emitter electrode at a ground potential and the collector electrode at a positive potential, the front 115 of the depletion layer extending from the pn junction 114 between the p-type base region 102 and the n-type drift layer 103 expands on the substrate surface while being stretched by a guard ring 113 surrounding the pn junction. As a result, an electric field on the substrate surface is relaxed. In addition, since a surface of the voltage blocking structure region 111 is protected by a protective film 116 of an insulation film, forward blocking capability is enhanced. On the other hand, if a reverse bias voltage of negative potential is applied on the collector electrode 109, a depletion layer (not shown in FIG. 12) begins to extend in the n-type drift layer from the pn junction 100 of the p-type collector layer 104 in the back surface side towards the emitter region 105. Since the peripheral end 101 of the pn junction 100 is exposed to the as-cut surface 112 created by a dicing process, a leakage current grows at the peripheral end 101, inhibiting reverse blocking with high reliability. In supplementary description on the reference numerals that are not mentioned in the above description on the IGBT, the reference numeral 110 represents an active region in which a main current flows, the numeral 106 represents a gate oxide film, and the numeral 107 represents a gate electrode.
Recently, a demand in the market for IGBTs having reverse blocking capability with high reliability is growing for applications to matrix converters and other systems. In order to meet the demand and improve reverse blocking capability and reliability of the conventional ordinary IGBT, a mesa type reverse blocking IGBT has been proposed as shown in FIG. 13 (Japanese Unexamined Patent Application Publication No. 2001-185727). This mesa type reverse blocking IGBT comprises a deep groove 122 formed by etching from the substrate surface beyond the collector pn junction 100, and a protective film 123 protects the peripheral end 101 of the pn junction exposed to the slanted inner surface of the groove. This structure prevents a front 117 of the depletion layer from extending to the dicing cut surface 112 located outside the groove and imparts reverse blocking capability with high reliability. This method, while serves a desired reverse blocking ability, needs a drift layer 103 of thick epitaxial layer (for example, a drift layer thickness of 100 μm and a thickness of the whole substrate of at least 250 μm for a breakdown voltage of 600 V), deteriorating a trade-off relationship between the saturation voltage Vce(sat) and the switching loss Eoff at the time of turn-off.
To cope with this problem, a reverse blocking IGBT of an isolated diffusion layer type as shown in FIG. 14 has been proposed (Japanese Unexamined Patent Application Publication No. 2002-319676) in which an isolated diffusion layer 121 is formed by impurity diffusion from the substrate surface to expose the peripheral end of the collector pn junction to the substrate surface and protect the end by an insulation film 116 commonly with the forward blocking structure region 111. This method allows fabricating a thin reverse blocking IGBT having an overall thickness of a semiconductor substrate of about 100 μm, substantially improving the trade-off relationship between the Vce(sat) and the switching loss Eoff at the time of turn-off. The reference numerals in FIG. 13 and FIG. 14 same as in FIG. 12 represent the same or corresponding functional regions as in FIG. 12.
In addition, a reverse blocking IGBT having ensuring both high forward blocking ability and high reverse blocking ability is known (Japanese Unexamined Patent Application Publication No. 2005-101254) in which the peripheral end of the reverse blocking junction is bent by an isolation diffusion layer to expose to the blocking structure region on the surface similar to the method of Japanese Unexamined Patent Application Publication No. 2002-319676 and further, a p-type field limiting ring (guard ring) structure and a conductive field plate structure are provided in the blocking structure region, the field plate protruding on an insulation film towards the center of the blocking structure region.
Another blocking structure for a bidirectional semiconductor device has been disclosed (Japanese Unexamined Patent Application Publication No. 2005-252212) in which a forward blocking structure region and a reverse blocking structure region are made to have an approximately equal width, wherein the forward blocking structure region alleviates electric field concentration on the substrate surface at the time of depletion layer extension from a main pn junction in a mostly emitter side, and the reverse blocking structure region alleviates electric field concentration at the time of depletion layer extension from a pn junction of the isolated diffusion layer like in Japanese Unexamined Patent Application Publication No. 2005-101254.
Concerning the reverse blocking devices, adequate studies have not been made enough on the optimum voltage blocking structure region. A length (a width on the surface) of the voltage blocking structure region conventionally tends to be made longer than a necessary length. A voltage blocking structure region disclosed in Japanese Unexamined Patent Application Publication No. 2005-252212 has approximately equal widths on the surface of the voltage blocking structure regions for a reverse blocking mode in which a depletion layer extends from a pn junction at the back surface collector layer and the isolation diffusion layer, and for a forward blocking mode in which a depletion layer extends from a main pn junction in the emitter side. In the reverse blocking mode, however, the depletion layer extends from the deep isolation diffusion layer and the whole of the back surface collector layer side. Thus, the length of the voltage blocking structure region does not need to be approximately equal to the length for the forward blocking mode in which the depletion layer extends solely from the emitter layer side. Consequently, there is a possibility to shorten the voltage blocking structure region for retaining the reverse blocking in which the depletion layer extends from the deep isolation diffusion layer and whole of the back surface collector region as compared with the width of the voltage blocking structure region for the forward blocking. As a result, if a width of the voltage blocking structure region for retaining the reverse blocking is made equal to the width of the voltage blocking structure region for the forward blocking (that is, the length of the voltage blocking structure region for the reverse blocking is made to be a length of a folded-back voltage blocking structure region for the forward blocking), the width of the voltage blocking structure region for the reverse blocking is longer than as needed. Therefore, such a configuration leads to an enlarged chip size and raised cost. On the contrary, if the voltage blocking structure regions are shortened for the purpose of reduction in the chip costs leaving the widths of the voltage blocking structure regions for the reverse blocking unchanged, it is very difficult to ensure satisfactory reliability of the device (for example, resistance to charges of the voltage blocking structure region). It is therefore very difficult to achieve compatibility between an appropriate chip cost and satisfactory reliability.